Juq016 Link =link= -

| Milestone | Target Date | Expected Enhancement | |-----------|-------------|----------------------| | (Second‑generation ASIC) | Q4 2026 | 30 % lower power, integrated on‑chip PLL. | | Multi‑Lane Scaling (×8) | H1 2027 | Aggregate bandwidth > 1.5 Tbps, targeted at large‑scale quantum simulators. | | Integrated Cryogenic Photonic Modulator | H2 2027 | Direct on‑chip conversion from microwave to optical, removing external converters. | | Standardization | 2028 | Submission of the IEEE 802.3cu‑JUQ draft to the IEEE 802.3 Working Group. | | Open‑Source Firmware | 2028 | Release of fully open firmware for the driver ASIC under BSD‑3‑Clause. |