iverilog -o multiplier_tb multiplier.v tb_multiplier.v vvp multiplier_tb gtkwave dump.vcd
(* use_dsp = "no" *) // Xilinx Specific Attribute module multiplier_8bit( input [7:0] A, input [7:0] B, output [15:0] P ); assign P = A * B; endmodule
iverilog -o multiplier_tb multiplier.v tb_multiplier.v vvp multiplier_tb gtkwave dump.vcd
(* use_dsp = "no" *) // Xilinx Specific Attribute module multiplier_8bit( input [7:0] A, input [7:0] B, output [15:0] P ); assign P = A * B; endmodule 8bit multiplier verilog code github
